/*
 * Copyright (c) 2021, Xilinx Inc. and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: MIT
 */
#define DEV_clk_wiz "/dev/uio10"
#define DEV_SIHA_Manager "/dev/uio11"
//#define DEV_AccelConfig_0 "/dev/uio4"
//#define DEV_dma_hls_0 "/dev/uio5"
//#define DEV_AccelConfig_1 "/dev/uio6"
//#define DEV_dma_hls_1 "/dev/uio7"
//#define DEV_AccelConfig_2 "/dev/uio8"
//#define DEV_dma_hls_2 "/dev/uio9"

const char * DEV_AccelConfig[]={"/dev/uio4", "/dev/uio6", "/dev/uio8"};
const char * DEV_dma_hls[]=    {"/dev/uio5", "/dev/uio7", "/dev/uio9"};


